Example embodiments of inventive concepts described herein relate to a semiconductor circuit, and in more detail, to a driver circuit charging a charge node.
A memory device includes a plurality of memory cells. A plurality of memory cells is regularly disposed according to a specific pattern to reduce an area occupied by the memory cells. The memory cells disposed according to a regular pattern may be connected to conductive lines for accessing the memory cells.
The memory device is highly integrated as the number of memory cells connected to each conductive line increases and a distance between conductive lines becomes shorter. In this case, a resistive load and a capacitive load of each conductive line increase. When the resistive load and the capacitive load increase, a lot of time is required to drive a voltage of a conductive line to a target level, and thus an operating speed of the memory device may decrease. Accordingly, there are required a device and a method capable of driving each conductive line with a target voltage quickly even though the resistive load and capacitive load of each conductive line increase.